This is done by exporting your SoC design out of Vivado IPI and into the Xilinx Software Development Kit (XSDK), an Integrated Development Environment (IDE) for designing/debugging MicroBlaze programs in C. The Arty A7 supports large MicroBlaze programs with demanding memory requirements by providing 16MB of non-volatile program memory and 256MB of DDR3L RAM.Īfter you design your soft SoC configuration for the Arty A7 you can start writing programs for it.
The MicroBlaze processor in an SoC configuration is typically run at 100 MHz, though it is possible to design your SoC so that it can operate at over 200MHz. MicroBlaze is a 32-bit RISC soft processor core, designed specifically to be used in Xilinx FPGAs. The Arty A7's Soft SoC configurations are powered by MicroBlaze processor cores. For those with no interest in learning HDL, the Xilinx High Level Synthesis tool can be used to define custom peripheral blocks by writing them in C. Ambitious users will also find that they can create their own peripheral blocks by writing them in a Hardware Definition Language (HDL), specifically Verilog or VHDL. These pre-built peripherals include timers, UART/SPI/IIC controllers, and many of the other devices you would typically find in an SoC or microcontroller. In this tool, pre-built peripheral blocks are dragged from an extensive library and dropped into your processing system as you see fit. These “Soft SoC” FPGA configurations are designed graphically using a tool called Vivado IP Integrator (Vivado IPI). Among their many features, FPGAs have the ability to transform into a custom software-defined System-on-a-Chip (SoC). What makes the Arty A7 so flexible is its FPGA. USB Scopes, Analyzers and Signal Generators.